Tianjun Bu (卜天峻)'s Homepage

Contact​

• email: butianjun2024##iscasaccn

About me​

I am currently a Master's student in the group. I explored various fields such as processing-in-memory and database systems before focusing on hardware verification, especially model checking engine optimization.

Education​

• Sept. 2024 – present: Master's student in Computer Science at Institute of Software, Chinese Academy of Sciences
• Sept. 2020 – June 2024: Bachelor's degree in Software Engineering from Nanjing University of Posts and Telecommunications

Publications​

1. Tianjun Bu, Zhichao Lyu and Qiusong Yang. Dropping Multiple Literals per SAT call in IC3 Model Checking. Proceedings of the 63rd ACM/IEEE Design Automation Conference (DAC), 2026.
2. Zhichao Lyu, Tianjun Bu and Qiusong Yang. Fast, transparent and accurate simulation of thousand processing-in-memory cores. Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2025.
3. Yuheng Su, Qiusong Yang, Yiwei Ci, Tianjun Bu and Ziyu Huang. The rIC3 hardware model checker. International Conference on Computer Aided Verification, 2025.