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17 posts tagged with "Thesis"

Thesis of versys group

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Paper on RISC-V ISA Conformance Model Checking Accepted at JSA'26

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We are proud that our paper "χRVFormal: Formal Verification of RISC-V Processor Chisel Designs", has been accepted at Journal of Systems Architecture (JSA) 2026.

χRVFormal presents the first end-to-end approach for formally verifying RISC-V processor designs entirely at the Chisel high-level. By constructing a modular, parameterized reference model in Chisel and devising a novel synchronization mechanism, it reduces verification to a model-checking problem applicable to both in-order and out-of-order processors. Evaluated on riscv-mini, NutShell, and BOOM, our tool significantly outperforms state-of-the-art methods, discovering 7 real-world unknown bugs and achieving three orders of magnitude higher efficiency.

Paper accepted at FM'26

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We are proud that our paper "Can LLM Aid in Solving Constraints with Inductive Definitions?", has been accepted at 27th Symposium on Formal Methods (FM) 2026.

Paper accepted at TDSC'26

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We are proud that our paper "AudioJailbreak: Jailbreak Attacks against End-to-End Large Audio-Language Models", has been accepted at IEEE Transactions on Dependable and Secure Computing (TDSC).

Paper accepted at FSE'26

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We are proud that our paper "SmartIFSyn: Automated Information Flow Security Policy Synthesis for Smart Contracts", has been accepted at ACM International Conference on the Foundations of Software Engineering (FSE) 2026.

Paper accepted at ESOP'26

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We are proud that our paper "A Formally Verified Procedure for Width Inference in FIRRTL", has been accepted at 35th European Symposium on Programming.

ESOP is an annual conference devoted to fundamental issues in the specification, design, analysis, and implementation of programming languages and systems, and is one of the conferences of ETAPS (European Joint Conferences on Theory and Practice of Software).